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Features
* EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed
to Store Configuration Programs for Programmable Gate Arrays
* Simple Interface to SRAM FPGAs Requires Only One User I/O Pin * Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs * Cascadable To Support Additional Configurations or Future Higher-Density Arrays * * * * * *
(17C128/256 only) Low-Power CMOS EEPROM Process Programmable Reset Polarity Available in Industry-Standard Pin-Compatible PLCC Package In-System Programmable via 2-Wire Bus Emulation of 24CXX Serial EEPROMs Available in 3.3V and 5V Versions
Description
The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configuration EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the popular 20-pin PLCC. The AT17A Series family uses a simple serial-access provides to configure one or more FPGA devices. The AT17A Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user can select the polarity of the reset function by programming a special EEPROM bit. The AT17A Series is pin compatible with the industry standard configurator, and can be programmed with industry standard programmers.
FPGA Configuration EEPROM
65K, 128K and 256K
AT17CxxxA AT17LVxxxA
Pin Configurations
20-Pin PLCC
NC DATA NC VCC NC 3 2 1 20 19 CE (nCS) GND NC CEO (nCASC) NC 9 10 11 12 13 CLK (DCLK) NC NC NC RESET/OE (RESET/OE) 4 5 6 7 8 18 17 16 15 14 SER_EN NC NC NC NC
Rev. 0996A-07/98
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Controlling The AT17A Series Serial EEPROMs
Most connections between the FPGA device and the serial EEPROM are simple and self-explanatory. * The DATA output of the AT17A Series drives DIN of the FPGA devices. * The master FPGA CCLK output drives the CLK input of the AT17A Series. * The CEO output of any AT17C/LV128/256A drives the CE input of the next AT17C/LV65/128/256 in a cascade chain of PROMs. * SER_EN must be connected to VCC. There are, however, two different ways to use the inputs CE and OE, as shown in the AC Characteristics waveforms. tion cycle. If a system reset is applied to the FPGA, it will abort the original configuration and then reset itself for a new configuration, as intended. Of course, the AT17A Series does not see the external reset signal and will not reset its internal address counters and, consequently, will remain out of sync with the FPGA for the remainder of the configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the AT17A Series, while its OE input is driven by the inversion of the input to the FPGA RESET input pin. This connection works under all normal circumstances, even when the user aborts a configuration before D/P has gone high. A high level on the RESET/OE input to the AT17C/LVxxxA - during FPGA reset - clears the Configurator's internal address pointer, so that the reconfiguration starts at the beginning. The AT17A Series does not require an inverter since the RESET polarity is programmable.
Condition 1
The simplest connection is to have the FPGA D/P output drive both CE and RESET/OE in parallel (Figure 1). Due to its simplicity, however, this method will fail if the FPGA receives an external reset condition during the configura-
Block Diagram
2
AT17A Series
AT17A Series
Pin Configurations
PLCC/S OIC Pin 2 4 8 DIP Pin 1 2 3 Name DATA CLK RESET/OE I/O I/O I Description Three-state DATA output for reading. Input/Output pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. RESET/Output Enable input (when SER_EN is High). A low level on both the CE and RESET/OE inputs enables the data output driver. A high level on RESET/OE resets both the address and bit counters. A logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE. I Chip Enable input. Used for device selection. A low level on both CE and OE enables the data output driver. A high level on CE disables both the address and bit counters and forces te device into a low-power mode. Note this pin will not enable/disable the device in 2-wire serial mode (ie; when SER_EN is low). Ground pin O Chip Enable Out output. This signal is asserted low on the clock cycle following the last bit read from the memory. It will stay low as long as CE and OE are both low. It will then follow CE until OE goes high. Thereafter, CEO will stay high until the entire PROM is read again and senses the status of RESET polarity. Device selection input, A2. This is used to enable (or select) the device during programming and when SER_EN is low (see Programming Guide for more details). Serial enable is normally high during FPGA loading operations. Bringing SER_EN low, enables the 2-wire serial interface for programming. +3.3V/+5V power supply pin.
9
4
CE
10 12
5 6
GND CEO
A2 18 20 7 8 SER_EN VCC
I I
Absolute Maximum Ratings*
Operating Temperature .................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground ............................. -0.1V to VCC + 0.5V Supply Voltage (VCC) .......................................-0.5 V to + 7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.) .............260C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode.
After configuration is complete, the address counters of all cascaded Configurators are reset if the reset signal drives the RESET/OE on each Configurator Active. If the address counters are not to be reset upon completion, then the RESET/OE inputs can be tied to ground. For more details, please reference the AT17C Series Programming Guide
Programming Mode
The programming mode is entered by bringing SER_EN low. In this mode the chip can be programmed by the 2wire interface. The programming is done at V CC supply only. Programming super voltages are generated inside the chip. See the Programming Specification for Atmel's Configuration Memories Application Note for further information. The AT17C Series parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.0V nominal.
Cascading Serial Configuration EEPROMs (AT17C/LV256A)
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory (17C/LV128/256A only). After the last bit from the first Configurator is read, the next clock signal to the Configurator asserts its CEO output Low and disables its DATA line. The second Configurator recognizes the low level on its CE input and enables its DATA output. Figure 1. Condition 1 Connection
M2 M1 M0 REBOOT FLEX 10K, FLEX 16K (CLK REQUIRED) SERIAL EEPROM D0 CCLK CS CON FLEX DEVICE RESET/OE AT17CXX DATA CLK CE SER_EN VCC
AT17C/LVxxx Reset Polarity
The AT17C/LVxxxA lets the user choose the reset polarity as either RESET/OE or RESET/OE.
Standby Mode
The AT17C/LVxxxA enters a low-power standby mode whenever CE is asserted high. In this mode, the Configurator consumes less than 1.0 mA of current. The output remains in a high-impedance state regardless of the state of the OE input.
FPGA
Operating Conditions
AT17Cxxx Symbol VCC Description Commercial Industrial Military Supply voltage relative to GND -0C to +70C Supply voltage relative to GND -40C to +85C Supply voltage relative to GND -55C to +125C Min/Max 4.75/5.25 4.5/5.5 4.5/5.5 AT17LVxxx Min/Max 3.0/3.6 3.0/3.6 3.0/3.6 Units V V V
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AT17A Series
AT17A Series
.
DC Characteristics
VCC = 5V 5% Commercial / 5V 10% Ind./Mil.
Symbol VIH VIL VOH VOL VOH VOL VOH VOL ICCA IL Description High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode Input or output leakage current (VIN = VCC or GND) Commercial Supply current, standby mode AT17C256 Industrial/Military ICCS Supply current, standby mode AT17C128/65 Industrial/Military 2 mA Commercial 150 1 -10 3.5 Military 0.4 10 10 75 V mA A A A mA 3.6 Industrial 0.37 V V Commercial 0.32 V V Min 2.0 0 3.7 Max VCC 0.8 Units V V V
DC Characteristics
VCC = 3.3V 10%
Symbol VIH VIL VOH VOL VOH VOL VOH VOL ICCA IL ICCS Description High-level input voltage Low-level input voltage High-level output voltage (IOH = -2.5 mA) Low-level output voltage (IOL = +3 mA) High-level output voltage (IOH = -2 mA) Low-level output voltage (IOL = +3 mA) High-level output voltage (IOH = -2 mA) Low-level output voltage (IOL = +2.5 mA) Supply current, active mode Input or output leakage current (VIN = VCC or GND) Commercial Supply current, standby mode Industrial/Military 100 -10 2.4 Military 0.4 5 10 50 V mA A A A 2.4 Industrial 0.4 V V Commercial 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 Units V V V
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AC Characteristics
AC Characteristics When Cascading
6
AT17A Series
AT17A Series
.
AC Characteristics for AT17C256A
VCC = 5V 5% Commercial / VCC = 5V 10% Ind./Mil
Commercial Symbol tOE
(2)
Industrial/Military Min Max 25 45 55 0 Units ns ns ns ns 50 20 20 40 0 20 12.5 ns ns ns ns ns ns MHz
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLk (to guarantee proper counting) OE High Time (guarantees counter is reset) MAX Input Clock Frequency
Min
Max 25 45 50
tCE(2) tCAC(2) tOH tDF tLC tHC tSCE tHCE tHOE FMAX
(2) (3)
0 50 20 20 35 0 20 12.5
.
AC Characteristics for AT17C256A When Cascading
VCC = 5V 5% Commercial / VCC = 5V 10% Ind./Mil
Commercial Symbol tCDF
(3)
Industrial/Military Min Max 50 40 35 35 Units ns ns ns ns
Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay
Min
Max 50 35 35 30
tOCK(2) tOCE(2) tOOE
(2)
Notes:
1. Preliminary specifications for military operating range only. 2. AC test load = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
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.
AC Characteristics for AT17C65/128A
VCC = 5V 5% Commercial / VCC = 5V 10% Ind./Mil.
Commercial Symbol tOE
(2)
Industrial/Military Min Max 150 50 55 0 Units ns ns ns ns 50 35 35 50 5 60 ns ns ns ns ns ns 10 MHz
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLk (to guarantee proper counting) OE High Time (guarantees counter is reset) MAX Input Clock Frequency
Min
Max 110 50 50
tCE(2) tCAC(2) tOH tDF tLC tHC tSCE tHCE tHOE FMAX(4)
(2) (3)
0 50 30 30 45 0 50 10
.
AC Characteristics for AT17C128/256A When Cascading
VCC = 5V 5% Commercial / VCC = 5V 10% Ind./Mil.
Commercial Symbol tCDF
(3)
Industrial/Military Min Max 50 75 60 55 Units ns ns ns ns
Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay
Min
Max 50 65 55 55
tOCK(2) tOCE(2) tOE
(2)
Notes:
1. Preliminary specifications for military operating range only. 2. AC test load = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels. 4. During cascade FMAX = 8 MHz.
8
AT17A Series
AT17A Series
AC Characteristics
VCC = 3.3V 10%
Commercial Symbol tOE
(2)
Industrial/Military Min Max 45 60 80 0 Units ns ns ns ns 55 25 25 60 0 25 ns ns ns ns ns ns 10 MHz
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLk (to guarantee proper counting) OE High Time (guarantees counter is reset) MAX Input Clock Frequency
Min
Max 40 60 75
tCE(2) tCAC(2) tOH tDF tLC tHC tSCE tHCE tHOE FMAX(4) Notes:
(2) (3)
0 55 25 25 35 0 25 10
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1. Preliminary specifications for military operating range only. 2. AC test lead = 50 pf. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels. 4. During cascade FMAX = 8 MHz.
AC Characteristics When Cascading
VCC = 3.3V 10%
Commercial Symbol tCDF(3) tOCK tOCE
(2) (2) (2)
Industrial/Military Min Max 60 60 60 45 Units ns ns ns ns
Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay
Min
Max 60 55 55 40
tOOE
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Ordering Information - 5V Devices
Memory Size (K) 64K Ordering Code AT17C65A-10JC AT17C65A-10JI 128K AT17C128A-10JC AT17C128A-10JI 256K AT17C256A-10JC AT17C256A-10JI Package 20J 20J 20J 20J 20J 20J Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Ordering Information - 3.3V Devices
Memory Size (K) 64K Ordering Code AT17LV65A-10JC AT17LV65A-10JI 128K AT17LV128A-10JC AT17LV128A-10JI 256K AT17LV256A-10JC AT17LV256A-10JI Package 20J 20J 20J 20J 20J 20J Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Package Type 20J 20-Lead, Plastic J-Leaded Chip Carrier (PLCC)
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AT17A Series
AT17A Series
Packaging Information
20J, 20-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AA
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